1. Field of the Invention
The invention relates to emitter follower type circuits also known as "common collector transistors", notably those made in the form of bipolar integrated circuits. It relates in particular to means for the polarization of emitter follower circuits.
2. Description of the Prior Art
The use of a bipolar transistor mounted as a "follower" (or "common collector") is very widespread, especially in analog electronic systems. Its chief characteristics are a voltage gain that is nearly unity, and a high current gain equal to B+1; B being the gain of the transistor equal to IC/IB (IC is the collector current, IB is the base current). The signal to be processed or input signal is applied to the base of the transistor and the corresponding output signal is delivered at the emitter. The variations of the output voltage VS on the emitter represent the input signal with a gain close to 1. The advantage of an assembly such as this is notably the fact that the output signal can be obtained with a high current. Its use sometimes raises difficulties, notably when it is sought to give a relatively high emitter bias current (often for reasons of speed constraints), which leads to the imposing of a base bias current which is itself relatively high.
FIGS. 1 and 2 use standard configurations to illustrate two cases where the voltage "read" at the base of the follower transistor is error-ridden because of the non-zero base current IB.
FIG. 1 illustrates the case of a voltage signal VG applied to the base B of a transistor T. The voltage signal VG is delivered by a voltage source SV. The corresponding output signal VS is delivered by the emitter E of the transistor T. The emitter E is connected to the ground potential by means of a current generator GI, in which there flows the emitter current IE of the transistor T. The collector C of the transistor T is connected to a supply potential VCC that is positive in relation to the ground.
The base current IB produces a voltage drop in the internal resistor RG of the source SV, in such a way that the voltage VB read at the base B is equal to VG-RG*IB.
FIG. 2 illustrates another example in which the capacitor Ca is positioned between the base of the follower transistor T and the ground. The transistor T is connected in a same way as in the above example as regards its collector C and its emitter E. This emitter represents a common configuration of follower transistors used for the reading of the sample-and-hold units. In a configuration such as this, the capacitor Ca is charged by a pulse at a voltage VG which decreases with time owing to the discharging of the capacitor C by the base current IB. The term used is that of the "drop-rate" of the voltage with reference to time.
A known way of circumventing the drawbacks related to the presence of the base bias current is to associate a bias circuit with the follower transistor, this bias circuit injecting an additional current into the base of the follower transistor. This additional current constitutes the base bias current which is thus not taken from the signal applied to the follower transistor.
It must be noted that the drawbacks illustrated with reference to FIGS. 1 and 2, due to the bias current in the base, also exist in the case of PNP type transistors.
FIG. 3 shows the diagram of a standard configuration associating a follower transistor T1 with a biasing circuit CP such as this.
As in the example of FIGS. 1 and 2, the collector C of the follower transistor T1 is connected to a first potential delivered by a voltage source with low internal resistance. This is a first voltage which, in the example, is a positive supply potential VCC. Its emitter E is connected to a second potential represented by the ground, by means of a current generator GI. The variations of the voltage VB on the base B of the follower transistor T1 are found again in the output voltage VS taken at the emitter E.
The current generator GI imposes an emitter current IE with the desired value on the follower transistor T1. To this emitter current IE there corresponds a base current IB injected by the biasing circuit CP.
The biasing circuit CP comprises two transistors T2, T3 mounted as a current mirror as well as a current generator circuit CGI. The current generator circuit imposes a collector current on the transistor T2. This collector current constitutes a replica IB' of the base current IB of the follower transistor T1.
This replica current is copied by the transistor T3 and injected into the base B of the follower transistor.
This constitutes an open-loop type of assembly that is easy to implement and that makes use, for the replica IB' of a transistor that is biased under conditions that are identical (or almost identical) to those of the follower transistor to be compensated for. Other assemblies are also used, but their implementation is more complicated. In these assemblies, a (closed) feedback loop is made, and this loop permanently compares the real base current and the replica current to make them equal.
These different assemblies have the common feature of using transistors of a type opposite that of the follower transistor to be biased, to obtain the base current IB to be injected into this follower transistor: for example, in the example of FIG. 3, the follower transistor T1 is of the NPN type while T2, T3 are of the PNP type. This is a first drawback when all that is available is a process with only one type of transistor. It must be recalled that, as a rule, making both PNP transistors and NPN transistors in one and the same process leads to an increase in manufacturing complexity and hence cost (especially if both types have to be matched in terms of speed). Another drawback, related to the types of biasing assemblies described here above, is that they have a parasitic collector capacitance at the input which causes deterioration in the characteristic input impedance of the assembly.